Low power cost-effective ECC memory system and method

ABSTRACT

A memory controller couples 32-bit data words to and from a DRAM. The DRAM generates error checking and correcting syndromes to check and correct read data. The DRAM generates the syndromes from respective 128-bit data words each formed by 4 32-bit data words written to the DRAM, and thereby achieves a low syndrome bit overhead. The memory controller may write data words to the DRAM having less than 128 bits by first reading 4 32-bit words from the DRAM, substituting the write data for a corresponding number of bits of read data, and writing the new 128-bit word to the DRAM by writing 4 32-bit words.

TECHNICAL FIELD

This invention relates to dynamic random access memory (“DRAM”) devices,and, more particularly, to a method and system for checking andcorrecting data read from memory devices in a manner that iscost-effective and consumes relatively little power.

BACKGROUND OF THE INVENTION

As the use of electronic devices, such as personal computers, continueto increase, it is becoming ever more important to make such devicesportable. The usefulness of portable electronic devices, such asnotebook computers, is limited by the limited length of time batteriesare capable of powering the device before needing to be recharged. Thisproblem has been addressed by attempts to increase battery life andattempts to reduce the rate at which such electronic devices consumepower.

Various techniques have been used to reduce power consumption inelectronic devices, the nature of which often depends upon the type ofpower consuming electronic circuits that are in the device. For example,electronic devices such a notebook computers, typically include dynamicrandom access memory (“DRAM”) devices that consume a substantial amountof power. As the data storage capacity and operating speeds of DRAMdevices continues to increase, the power consumed by such devices hascontinued to increase in a corresponding manner.

In general, the power consumed by a DRAM device increases with both thecapacity and the operating speed of the DRAM devices. The power consumedby DRAM devices is also affected by their operating mode. A DRAM devicefor example, will generally consume a relatively large amount of powerwhen the memory cells of the DRAM device are being refreshed. As iswell-known in the art, DRAM memory cells, each of which essentiallyconsists of a capacitor, must be periodically refreshed to retain datastored in the DRAM device. Refresh is typically performed by essentiallyreading data bits from the memory cells in each row of a memory cellarray and then writing those same data bits back to the same cells inthe row. A relatively large amount of power is consumed when refreshinga DRAM because rows of memory cells in a memory cell array are beingactuated in the rapid sequence. Each time a row of memory cells isactuated, a pair of digit lines for each memory cell are switched tocomplementary voltages and then equilibrated. As a result, DRAMrefreshes tends to be particularly power-hungry operations. Further,since refreshing memory cells must be accomplished even when the DRAM isnot being used and is thus inactive, the amount of power consumed byrefresh is a critical determinant of the amount of power consumed by theDRAM over an extended period. Thus many attempts to reduce powerconsumption in DRAM devices have focused on reducing the rate at whichpower is consumed during refresh.

Refresh power can, of course, be reduced by reducing the rate at whichthe memory cells in a DRAM are being refreshed. However, reducing therefresh rate increases the risk that data stored in the DRAM memorycells will be lost. More specifically, since, as mentioned above, DRAMmemory cells are essentially capacitors, charge inherently leaks fromthe memory cell capacitors, which can change the value of a data bitstored in the memory cell over time. However, current leaks fromcapacitors at varying rates. Some capacitors are essentiallyshort-circuited and are thus incapable of storing charge indicative of adata bit. These defective memory cells can be detected during productiontesting, and can then be repaired by substituting non-defective memorycells using conventional redundancy circuitry. On the other hand,current leaks from most DRAM memory cells at much slower rates that spana wide range. A DRAM refresh rate is chosen to ensure that all but a fewmemory cells can store data bits without data loss. This refresh rate istypically once every 64 ms. The memory cells that cannot reliably retaindata bits at this refresh rate are detected during production testingand replaced by redundant memory cells.

One technique that has been used to prevent data errors during refreshas well as at other times is to generate an error correcting code “ECC,”which is known as a “syndrome,” from each item of stored data, and thenstore the syndrome along with the data. When the data are read from thememory device, the syndrome is also read, and it is then used todetermine if any bits of the data are in error. As long as not too manydata bits are in error, the syndrome may also be used to correct theread data.

A computer system 10 employing typical ECC techniques is shown inFIG. 1. The computer system 10 includes a central processor unit (“CPU”)14 coupled to a system controller 16 through a processor bus 18. Thesystem controller 16 is coupled to input/output (“I/O”) devices (notshown) through a peripheral bus 20 and to an I/O controller 24 throughan expansion bus 26. The I/O controller 24 is also connected to variousperipheral devices (not shown) through an I/O bus 28.

The system controller 16 includes a memory controller 30 that is coupledto a dynamic random access memory (“DRAM”) 32 through an address bus 36,a control bus 38, a syndrome bus 40, and a data bus 42. The DRAM 32includes an array 34 of memory cells that stores data and a syndromecoupled through the data bus 42 and the syndrome bus 40, respectively.The locations in the DRAM 32 to which data are written and data are readare designated by addresses coupled to the DRAM 32 on the address bus36. The operation of the DRAM is controlled by control signals coupledto the DRAM 32 on the control bus 38.

In operation, when data are to be written to the DRAM 32, the memorycontroller 30 generates a syndrome and then couples the syndrome and thewrite data to the DRAM 32 through the syndrome bus 40 and the data bus42, respectively. The memory controller 30 also couples control signalsto the DRAM 32 through the control bus 38 and a memory address throughthe address bus 36. The data are then stored in an array 34 of DRAMmemory cells. When the stored data are to be read from the DRAM 32, thememory controller 30 applies control signals to the DRAM 32 through thecontrol bus 38 and a memory address to the DRAM 32 through the addressbus 36. Read data and the corresponding syndrome are then coupled fromthe DRAM 32 to the memory controller 30 through the data bus 42 andsyndrome bus 40, respectively. The memory controller 30 then uses thesyndrome to determine if any bits of the read data are in error, if nottoo many bits are in error, to correct the read data.

The use of ECC techniques can significantly improve the reliability ofdata stored in the DRAM 32. Furthermore, the use of ECC techniques canallow the DRAM to be refreshed at a slower refresh rate since resultingdata bit errors can be corrected. The use of a slower refresh rate canprovide the significant advantage of reducing the power consumed by theDRAM 32. However, the need to perform ECC processing on read data allduring refresh can consume a significant amount of power. Further, theuse of ECC techniques requires that a significant portion of the DRAMstorage capacity be used to store the syndromes, thus requiring that thesize of the DRAM semiconductor die be increased to maintain the storagecapacity of the DRAM 32. Further, to the extent that power is requiredto store the syndromes, the use of ECC techniques can increase powerconsumption. The amount of power consumed by storage of the syndromeeach time data are written to the DRAM 32 is a function of the number ofbits in the syndrome. The size of the syndrome needed to correct singlebit errors is determined by the number of bits in the data being checkedand corrected, and is given by the following table: TABLE 1 Data BitsSyndrome Bits Syndrome Bit Overhead 8 4 50% 16 5 31% 32 6 19% 64 7 11%128 8  6%In general, the syndrome bit overhead, expressed as the ratio of thenumber of necessary syndrome bits (i.e., N+1) to the number of data bits(i.e., 2^(N)), is equal to (N+1)/2^(N). As the numerator increaseslinearly with N and the denominator increases geometrically with N, itis apparent that significantly greater efficiencies can be achieved withhigher values of N, i.e., syndromes generated from a greater number ofdata bits. However, memory controllers generally do not write data toDRAMs or read data from DRAMs using very wide data paths. For example,in the computer system 10 shown in FIG. 1, the data bus 42 has a widthof only 32 bits, and a 32-bit word would require 6 syndrome bits, whichwould result in a 16% syndrome overhead. As a result, the extent towhich syndrome bit overhead can be reduced is very limited.

There is therefore a need for a memory system and method that detectsand corrects errors in data stored in DRAMs while consuming relativelylittle power and consuming relatively little space on a semiconductordie, and which does not require substantial modifications in theoperation of memory controllers that are coupled to the DRAMS.

SUMMARY OF THE INVENTION

An error checking and correcting memory device and method includeson-board circuitry for generating a syndrome from the data written tothe memory device. The syndrome is generated from more bits of writedata than the number of write data bits that can be simultaneouslycoupled to the memory device. More specifically, the syndrome isgenerated from several write data words that are sequentially coupled tothe memory device. The memory device uses the syndrome to check andcorrect any data that are read from the memory device. The use of datahaving a large number of bits to generate the syndrome allows thesyndrome bit overhead to be relatively low so that a significant amountof storage capacity is not used to store the syndrome.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a conventional computer system.

FIG. 2 is a block diagram of a computer system according to oneembodiment of the invention.

FIG. 3 is a flow chart showing the manner in which a partial data wordis written in the computer system of FIG. 2 to allow a syndrome to begenerated based on a full word.

FIG. 4 is a timing diagram showing signals used to perform the operationshown in FIG. 3.

FIG. 5 is a block diagram of a memory device according to one embodimentof the invention that may be used in the computer system of FIG. 2.

FIG. 6 is a block diagram showing a portion of the memory device of FIG.5 in greater detail.

DETAILED DESCRIPTION

A computer system 100 according to one embodiment of the invention isshown in FIG. 2. The computer system 100 uses many of the samecomponents that are used in the conventional computer system 10 ofFIG. 1. Therefore, in the interest of brevity, these components havebeen provided with the same reference numerals, and an explanation oftheir operation will not be repeated. The computer system 100 of FIG. 2differs from the computer system 10 of FIG. 1 by including a DRAM 102that includes a syndrome memory 120 and ECC logic 110, and by omitting asyndrome bus. The ECC logic 110 generates a syndrome from write datareceived from the memory controller 30, and stores the syndrome in thesyndrome memory 120 while the write data are being stored in the DRAMarray 34. When data are read from the DRAM array 34, the read data arecoupled from the array 34 to the ECC logic 110 and the syndrome arecoupled from the syndrome memory 120 to the ECC logic 110. The ECC logic110 then uses the syndrome to determine if the read data contains anerroneous data bit, and, if more than one data bit is not in error, tocorrect the erroneous data bit. The corrected read data are then coupledto the memory controller 30 through the data bus 42. Although thesyndrome memory 120 may be a separate memory as shown in FIG. 2, it mayalternatively be included in the DRAM array 34, as explained in greaterdetail below.

The DRAM 102 is able to use ECC techniques with relatively littlesyndrome bit overhead by generating syndromes from a relatively widedata word. In one embodiment of the invention, a data bus 42 having awidth of 32 bits is used. However, in that embodiment, the ECC logic 110generates syndromes from 128-bit data words. Therefore, every writerequires that 4 32-bit words be coupled through the data bus 42. Asshown in Table 1, the 128 bit word requires a syndrome of only 8 bits,which achieves a syndrome bit overhead of only 6 percent.

As mentioned above, the ECC logic 110 generates syndromes from 128-bitdata words, but the memory controller 30 often writes data to the DRAM102 in bytes consisting of 8 bits or some other number of bits less than128 bits. To solve this problem the computer system 100 operates in amanner that allows the ECC logic 110 to generate a syndrome when only 8bits, or data having less than 128 bits, are being written to the DRAM102. The manner in which the computer system 100 operates in this mannerwill now be explained with reference to a flow chart 200 shown in FIG. 3and a timing diagram shown in FIG. 4. In explaining the operation of thecomputer system 100, the assumption will be made that the data bus 42has a width of 32 bits, and the CPU 14 is writing a partial word of 8bits. With reference to FIG. 3, the partial word write 200 is entered at204 when the CPU 14 places a write (“WR”) command on the CPU bus 18, asshown in FIG. 4. The memory controller 30 then reads the entire 128-bitword that encompasses the address to which the 8-bits are to be writtenat step 206. This read is accomplished by the memory controller 30coupling an active row command (“ACT”) to the DRAM 102 through thecontrol bus 38, as shown in FIG. 4. Four 32-bit words that encompass the128-bit word are then coupled from the DRAM 102 to the memory controller30 through the data bus 42 responsive to four read (“RD”) commandscoupled through the control bus 38. The 8-bits bits to be written to theDRAM 102 are then substituted for corresponding bits in one of the32-bit words read from the DRAM 102 at step 210. The memory controller30 then formulates a new 128-bit word from three of the 32-bit wordsthat were read from the DRAM 102 and the new 32-bit word containing the8 new bits and 24 bits read from the DRAM 102. After an idle period(“Idle”) shown in FIG. 4, the new 128-bit word is written to the DRAM102 at step 214 by coupling 4 write commands (“WR”) to the DRAM 102through the control bus 38, as also shown in FIG. 4. The ECC logic 110receives the 4 32-bit words that constitute the 128-bit word, generatesan 8-bit syndrome from the 128-bit word. The 128-bit word is thenwritten to the DRAM array 34 and the 8-bit syndrome is written to thesyndrome memory 120. The computer system then returns to normaloperation through step 216.

Although the operation of the computer system 100 has been explained inthe context of a system 100 having a 32-bit data bus 42 and ECC logicthat generates a syndrome from 128-bit data words formed by 4 32-bitwords, it will be understood that computer systems may use data buseshaving different widths, and the word from which the syndrome is formed,which may be other than 128 bits, may be formed by a lesser or greaternumber of smaller words, such as words having 32-bits.

A synchronous DRAM (“SDRAM”) 300 according to one embodiment of theinvention is shown in FIG. 5. The SDRAM 300 includes an address register312 that receives bank addresses, row addresses and column addresses onan address bus 314. The address bus 314 is generally coupled to a memorycontroller (not shown in FIG. 5). Typically, a bank address is receivedby the address register 312 and is coupled to bank control logic 316that generates bank control signals, which are described further below.The bank address is normally coupled to the SDRAM 300 along with a rowaddress. The row address is received by the address register 312 andapplied to a row address multiplexer 318. The row address multiplexer318 couples the row address to row address latch & decoder circuit 320a-d for each of several banks of memory cell arrays 322 a-d,respectively. Each bank 320 a-d is divided into two sections, a datasecond 324 that is used for storing data, and a syndrome section 326that is used for storing syndromes. Thus, unlike the SDRAM 102 of FIG.2, a separate syndrome memory 120 is not used in the SDRAM 300 of FIG.5.

One of the latch & decoder circuits 320 a-d is enabled by a controlsignal from the bank control logic 316 depending on which bank of memorycell arrays 322 a-d is selected by the bank address. The selected latch& decoder circuit 320 applies various signals to its respective bank 322as a function of the row address stored in the latch & decoder circuit320. These signals include word line voltages that activate respectiverows of memory cells in the banks 322. The row address multiplexer 318also couples row addresses to the row address latch & decoder circuits320 a-d for the purpose of refreshing the memory cells in the banks 322a-d. The row addresses are generated for refresh purposes by a refreshcounter 330. During operation in a self-refresh mode, the refreshcounter 330 periodically begins operating at times controlled by aself-refresh timer 332.

After the bank and row addresses have been applied to the addressregister 312, a column address is applied to the address register 312.The address register 312 couples the column address to a column addresscounter/latch circuit 334. The counter/latch circuit 334 stores thecolumn address, and, when operating in a burst mode, generates columnaddresses that increment from the received column address. In eithercase, either the stored column address or incrementally increasingcolumn addresses are coupled to column address & decoders 338 a-d forthe respective banks 322 a-d. The column address & decoders 338 a-dapply various signals to respective sense amplifiers 340 a-d and 342 a-dthrough column interface circuitry 344. The column interface circuitry344 includes conventional I/O gating circuits, DQM mask logic, read datalatches for storing read data from the memory cells in the banks 322 andwrite drivers for coupling write data to the memory cells in the banks322. The column interface circuitry 344 includes the ECCgenerator/checker 346 that is the ECC logic 110 in the DRAM 102 of FIG.2.

Syndromes read from the syndrome section 326 of one of the banks 322 a-dare sensed by the respective set of sense amplifiers 340 a-d and thencoupled to the ECC generator checker 346. Data read from the datasection 324 one of the banks 322 a-d are sensed by the respective set ofsense amplifiers 342 a-d and then stored in the read data latches in thecolumn interface circuitry 344. The data are then coupled to a dataoutput register 348, which applies the read data to a data bus 350. Datato be written to the memory cells in one of the banks 322 a-d arecoupled from the data bus 350 through a data input register 352 to writedrivers in the column interface circuitry 344. The write drivers thencouple the data to the memory cells in one of the banks 322 a-d. A datamask signal “DQM” is applied to the column interface circuitry 344 andthe data output register 348 to selectively alter the flow of data intoand out of the column interface circuitry 344, such as by selectivelymasking data to be read from the banks of memory cell arrays 322 a-d.

The above-described operation of the SDRAM 300 is controlled by controllogic 356, which includes a command decoder 358 that receives commandsignals through a command bus 360. These high level command signals,which are typically generated by a memory controller (not shown in FIG.5), are a clock a chip select signal CS#, a write enable signal WE#, acolumn address strobe signal CAS#, and a row address strobe signal RAS#,with the “#” designating the signal as active low. Various combinationsof these signals are registered as respective commands, such as a readcommand or a write command. The control logic 356 also receives a clocksignal CLK and a clock enable signal CKE#, which cause the SDRAM 300 tooperate in a synchronous manner. The control logic 356 generates asequence of control signals responsive to the command signals to carryout the function (e.g., a read or a write) designated by each of thecommand signals. The control logic 356 also applies signals to therefresh counter 330 to control the operation of the refresh counter 330during refresh of the memory cells in the banks 322. The control signalsgenerated by the control logic 356, and the manner in which theyaccomplish their respective functions, are conventional. Therefore, inthe interest of brevity, a further explanation of these control signalswill be omitted.

The control logic 356 also includes a mode register 364 that may beprogrammed by signals coupled through the command bus 360 duringinitialization of the SDRAM 300. The mode register 364 then generatesmode control signals that are used by the control logic 356 to controlthe operation of the SDRAM 300 in various modes. Finally, the controllogic 356 also includes an ECC controller 370 that causes the controllogic 356 to issue control signals to the ECC generator checker 346 andother components to generate syndromes for storage in the syndromesection 326 of the banks 322 a-d, and to check and correct data readfrom the data section 324 of the banks 322 a-d using syndromes stored inthe sections 326.

The interfaces between the sense amplifiers 340, 342, the ECCgenerator/checker 346 and certain components in the column interfacecircuitry 344 are shown in greater detail in FIG. 6. The senseamplifiers 342 coupled to the data sections 342 of the memory banks 322a-d output respective data bits for respective columns, which areapplied to column steering logic 380. In the embodiment shown in FIG. 6,the sense amplifiers 342 output respective data bits for 8,192 columns.The column steering logic 380 uses the 6 most significant bits 2-7 of acolumn address to select 1 of 64 128-bit groups of data bits and couplesthe data bits to the ECC generator/checker 346. The sense amplifiers 340coupled to the syndrome section of the memory banks 322 a-d couple asyndrome corresponding to the read data directly to the ECCgenerator/checker 346.

The ECC generator/checker 346 includes a comparator 384 that provides anerror indication in the event the read data contains an error. The ECCgenerator/checker 346 then couples the corrected 128-bit word toadditional column steering logic 388, and also couples the corrected128-bit word back through the column steering logic 380 to the banks 322a-d so that the banks will now contain correct data. The column steeringlogic 388 uses the 2 least significant bits 0-1 of a column address toselect 1 of 4 32-bit groups of data bits and couples the data bits tothe memory controller 30 (FIG. 2), as previously explained. It is notnecessary for the column steering logic 388 to couple the syndrome tothe memory controller 30 so that the operation error checking andcorrection function is transparent to the memory controller 30. Also,although 128 bits of write data are used to form the syndrome, it is notnecessary for the memory device 102 to include externally accessibledata terminals for each of these 128 bits.

Although the present invention has been described with reference to thedisclosed embodiments, persons skilled in the art will recognize thatchanges may be made in form and detail without departing from the spiritand scope of the invention. For example, although the 128-bit write dataword has been described of as being formed from 96 bits of read data and8 bits of new write data, it will be understood that the 128-bit writedata may be formed by other means.

1. A method of reading data from and writing data to a memory devicehaving an array of memory cells, comprising: coupling a memory writecommand to the memory device; coupling at least one M-bit word of writedata to the memory device, where M is a positive integer; within thememory device, using N of the M-bit words to generate an error checkingand correcting syndrome, where N is a positive integer greater than one;coupling at least a portion of the N M-bit words to the array of memorycells; storing the generated syndrome in the memory device; coupling amemory read command to the memory device; in response to the readcommand, coupling N M-bit words from the array of memory cells; withinthe memory device, using a syndrome corresponding to the N M-bit wordscoupled from the array of memory cells to determine if any of the bitsof the N M-bit words coupled from the array of memory cells is in error;if any of the bits of the N M-bit words are determined to be in error,using the syndrome to correct each erroneous bit and provide corrected NM-bit words, and coupling at least one of the corrected N M-bit wordsfrom the memory device; and if any of the bits of the N M-bit words arenot determined to be in error, coupling at least one of the N M-bitwords coupled from the array of memory cells from the memory device. 2.The method of claim 1 wherein the act of coupling at least one M-bitword of write data to the memory device comprises: reading P M-bit wordsfrom the memory device, where P is a positive integer; combining the PM-bit words read from the memory device with N minus P M-bit words tocreate N M-bit words; and coupling the created N M-bit words to thememory device.
 3. The method of claim 2 wherein M is equal to 32, N isequal to 4, and P is equal to
 3. 4. The method of claim 1 wherein theact of coupling at least one M-bit word of write data to the memorydevice comprises coupling N M-bit words of write data to the memorydevice.
 5. The method of claim 4 wherein M is equal to 32, and N isequal to
 4. 6. The method of claim 1 wherein the act of coupling atleast a portion of the N M-bit words to the array of memory cellscomprises coupling all N M-bit words to the array of memory cells. 7.The method of claim 1 wherein the act of storing the generated syndromein the memory device comprises storing the generated syndrome in thesame array of memory cells to and from which the N M-bits words arecoupled.
 8. The method of claim 1 wherein the act of storing thegenerated syndrome in the memory device comprises storing the generatedsyndrome in a storage device that is separate from the array of memorycells.
 9. The method of claim 1 wherein M is equal to 32, and N is equalto
 4. 10. The method of claim 1, further comprising coupling thecorrected N M-bit words to the array of memory cells so that correcteddata can be stored in the memory device.
 11. The method of claim 1wherein the act of coupling at least one of the corrected N M-bit wordsfrom the memory device comprises coupling all N of the corrected N M-bitwords from the memory device.
 12. The method of claim 1 wherein the actof coupling at least one of the N M-bit words coupled from the array ofmemory cells from the memory device comprises coupling all N of the NM-bit words coupled from the array of memory cells from the memorydevice.
 13. The method of claim 1 wherein the memory device having anarray of memory cells comprises a DRAM memory device having an array ofDRAM memory cells.
 14. A method of reading data from a memory devicehaving an array of memory cells, comprising: coupling a memory readcommand to the memory device; in response to the read command, couplingN M-bit words from the array of memory cells; within the memory device,using a syndrome corresponding to the N M-bit words coupled from thearray of memory cells to determine if any of the bits of the N M-bitwords coupled from the array of memory cells is in error; if any of thebits of the N M-bit words are determined to be in error, using thesyndrome to correct each erroneous bit and provide corrected N M-bitwords, and coupling at least one of the corrected N M-bit words from thememory device; and if any of the bits of the N M-bit words are notdetermined to be in error, coupling at least one of the N M-bit wordscoupled from the array of memory cells from the memory device.
 15. Themethod of claim 14 wherein M is equal to 32, and N is equal to
 4. 16.The method of claim 14, further comprising coupling the corrected NM-bit words to the array of memory cells so that corrected data can bestored in the memory device.
 17. The method of claim 14 wherein the actof using a syndrome corresponding to the N M-bit words coupled from thearray of memory cells to determine if any of the bits of the N M-bitwords coupled from the array of memory cells is in error comprises:coupling the syndrome from a storage device within the memory device;and using the syndrome coupled from a storage device within the memorydevice to determine if any of the bits of the N M-bit words coupled fromthe array of memory cells is in error.
 18. The method of claim 17wherein the act of coupling the syndrome from a storage device withinthe memory device comprises coupling the syndrome from the same array ofmemory cells from which the N M-bits words are coupled.
 19. The methodof claim 17 wherein the act of coupling the syndrome from a storagedevice within the memory device comprises coupling the syndrome from astorage device that is separate from the array of memory cells fromwhich the N M-bits words are coupled.
 20. The method of claim 14 whereinthe act of coupling at least one of the corrected N M-bit words from thememory device comprises coupling all N of the corrected N M-bit wordsfrom the memory device.
 21. The method of claim 14 wherein the act ofcoupling at least one of the N M-bit words coupled from the array ofmemory cells from the memory device comprises coupling all N of the NM-bit words coupled from the array of memory cells from the memorydevice.
 22. The method of claim 14 wherein the memory device having anarray of memory cells comprises a DRAM memory device having an array ofDRAM memory cells.
 23. A method of writing data to a memory devicehaving an array of memory cells, comprising: coupling a memory writecommand to the memory device; coupling at least one M-bit word of writedata to the memory device, where M is a positive integer; within thememory device, using N of the M-bit words to generate an error checkingand correcting syndrome, where N is a positive integer greater than one;coupling at least a portion of the N M-bit words to the array of memorycells; and storing the generated syndrome in the memory device.
 24. Themethod of claim 23 wherein the act of coupling at least one M-bit wordof write data to the memory device comprises: reading P M-bit words fromthe memory device, where P is a positive integer; combining the P M-bitwords read from the memory device with N minus P M-bit words to create NM-bit words; and coupling the created N M-bit words to the memorydevice.
 25. The method of claim 24 wherein M is equal to 32, N is equalto 4, and P is equal to
 3. 26. The method of claim 23 wherein the act ofcoupling at least one M-bit word of write data to the memory devicecomprises coupling N M-bit words of write data to the memory device. 27.The method of claim 26 wherein M is equal to 32, and N is equal to 4.28. The method of claim 23 wherein the act of coupling at least aportion of the N M-bit words to the array of memory cells comprisescoupling all N M-bit words to the array of memory cells.
 29. The methodof claim 23 wherein the act of storing the generated syndrome in thememory device comprises storing the generated syndrome in the same arrayof memory cells to which the N M-bits words are coupled.
 30. The methodof claim 23 wherein the act of storing the generated syndrome in thememory device comprises storing the generated syndrome in a storagedevice that is separate from the array of memory cells.
 31. The methodof claim 23 wherein M is equal to 32, and N is equal to
 4. 32. Themethod of claim 23 wherein the memory device having an array of memorycells comprises a DRAM memory device having an array of DRAM memorycells.
 33. A method of storing and correcting data in a memory device,comprising: writing data to the memory device; generating an errorchecking and correcting syndrome in the memory device from the datawritten to the memory device, the syndrome being generated from writedata having more bits than the number of write data bits that can besimultaneously coupled to the memory device; and using the syndrome tocheck and correct any data read from the memory device.
 34. The methodof claim 33, further comprising using the syndrome to correct the datastored in the memory device.
 35. The method of claim 33, furthercomprising storing the generated syndrome within the memory device, andwherein the act of using the syndrome to check and correct any data readfrom the memory device comprises retrieving the stored syndrome andusing the retrieved syndrome to check and correct any data read from thememory device.
 36. The method of claim 35 wherein the act of storing thegenerated syndrome within the memory device comprises storing thegenerated syndrome in an array of memory cells in which the data writtento the memory device are stored.
 37. The method of claim 35 wherein theact of storing the generated syndrome within the memory device comprisesstoring the generated syndrome in a storage device that is separate froman array of memory cells in which the data written to the memory deviceare stored.
 38. The method of claim 33 wherein the memory devicecomprises a DRAM memory device.
 39. A memory device, comprising: anarray of memory cells arranged in rows and columns; an address decoderreceiving row addresses and column addresses, the address decoder beingoperable to activate a row of memory cells corresponding to eachreceived row address and to select a memory cell in a column of memorycells corresponding to each received column address; a read data pathoperable to couple read data from selected memory cells in an activatedrow to a plurality of data bus terminals; a write data path operable tocouple write data from the plurality of data bus terminals to selectedmemory cells in an activated row; error checking and correcting logiccoupled to the read data path and the write data path, the errorchecking and correcting logic being operable to generate an errorchecking and correcting syndrome in the memory device from the datawritten to the memory device, the syndrome being generated from morewrite data bits than the number of data bus terminals, the errorchecking and correcting logic further being operable to use the syndrometo check and correct the data read coupled to the data bus terminals;and control logic operable to cause the write data to be coupled fromthe data bus terminals to the array of memory cells and to cause theread data to be coupled from the array of memory cells to the data busterminals.
 40. The memory device of claim 39, further comprising asyndrome memory coupled to the error checking and correcting logic, thesyndrome memory receiving and storing the generated an error checkingand correcting syndrome and coupling the stored error checking andcorrecting syndrome to the error checking and correcting logic so thatthe error checking and correcting logic can use the syndrome to checkand correct the data read coupled to the data bus terminals.
 41. Thememory device of claim 40 wherein the syndrome memory comprises thearray of memory cells to which the write data are written and the readdata are read.
 42. The memory device of claim 40 wherein the syndromememory comprises a storage device that is separate from the array ofmemory cells to which the write data are written and the read data areread.
 43. The memory device of claim 39 wherein the memory devicecomprises a dynamic random access memory device.
 44. The memory deviceof claim 39 wherein the read data path comprises column interfacecircuitry containing the error checking and correcting logic.
 45. Thememory device of claim 44 wherein the column interface circuitrycomprises: a first set of column steering logic coupled to the array ofmemory cells, the first set of column steering logic being operable toselect a subset of read data bits from a corresponding subset of columnsof the array of memory cells and to couple the selected subset of readdata bits to the error checking and correcting logic; and a second setof column steering logic coupled to the error checking and correctinglogic, the second set of column steering logic being operable to selecta subset of read data bits from the subset of read data bits selected bythe first set of column steering logic and coupled to the error checkingand correcting logic.
 46. The memory device of claim 39 wherein thecontrol logic comprises an error checking and correcting controllercoupled to the error checking and correcting logic for controlling theoperation of the error checking and correcting logic.
 47. A computersystem, comprising: a processor; a memory device, comprising: an arrayof memory cells arranged in rows and columns; an address decoderreceiving row addresses and column addresses, the address decoder beingoperable to activate a row of memory cells corresponding to eachreceived row address and to select a memory cell in a column of memorycells corresponding to each received column address; a read data pathoperable to couple read data from selected memory cells in an activatedrow to a plurality of data bus terminals; a write data path operable tocouple write data from the plurality of data bus terminals to selectedmemory cells in an activated row; error checking and correcting logiccoupled to the read data path and the write data path, the errorchecking and correcting logic being operable to generate an errorchecking and correcting syndrome in the memory device from the datawritten to the memory device, the syndrome being generated from morewrite data bits than the number of data bus terminals, the errorchecking and correcting logic further being operable to use the syndrometo check and correct the data read coupled to the data bus terminals;and control logic operable to cause the write data to be coupled fromthe data bus terminals to the array of memory cells and to cause theread data to be coupled from the array of memory cells to the data busterminals; and a memory controller coupled to the processor and to thememory device, the memory controller being operable to cause the memorydevice to write data applied to the data bus terminals of the memorydevice and to read data that is coupled from the data bus terminals ofthe memory device.
 48. The computer system of claim 47, furthercomprising a syndrome memory coupled to the error checking andcorrecting logic, the syndrome memory receiving and storing thegenerated an error checking and correcting syndrome and coupling thestored error checking and correcting syndrome to the error checking andcorrecting logic so that the error checking and correcting logic can usethe syndrome to check and correct the data read coupled to the data busterminals.
 49. The computer system of claim 48 wherein the syndromememory comprises the array of memory cells to which the write data arewritten and the read data are read.
 50. The computer system of claim 48wherein the syndrome memory comprises a storage device that is separatefrom the array of memory cells to which the write data are written andthe read data are read.
 51. The computer system of claim 47 wherein thememory device comprises a dynamic random access memory device.
 52. Thecomputer system of claim 47 wherein the read data path comprises columninterface circuitry containing the error checking and correcting logic.53. The computer system of claim 52 wherein the column interfacecircuitry comprises: a first set of column steering logic coupled to thearray of memory cells, the first set of column steering logic beingoperable to select a subset of read data bits from a correspondingsubset of columns of the array of memory cells and to couple theselected subset of read data bits to the error checking and correctinglogic; and a second set of column steering logic coupled to the errorchecking and correcting logic, the second set of column steering logicbeing operable to select a subset of read data bits from the subset ofread data bits selected by the first set of column steering logic andcoupled to the error checking and correcting logic.
 54. The computersystem of claim 47 wherein the control logic comprises an error checkingand correcting controller coupled to the error checking and correctinglogic for controlling the operation of the error checking and correctinglogic.
 55. A memory system, comprising: a memory controller operable tooutput memory write commands and memory read commands, and to transmitat least one M-bit word of write data and to receive at least one M-bitword of read data, where M is a positive integer; a memory devicecoupled to the memory controller, the memory device comprising: an arrayof memory cells; an address decoder receiving row addresses and columnaddresses from the memory controller, the address decoder being operableto activate a row of memory cells corresponding to each received rowaddress and to select a memory cell in a column of memory cellscorresponding to each received column address; a read data path operableto couple the at least one M-bit word of read data from selected memorycells in an activated row to the memory controller; a write data pathoperable to couple the at least one M-bit word of write data from thememory controller to selected memory cells in an activated row; errorchecking and correcting logic coupled to the read data path and thewrite data path, the error checking and correcting logic being operableto generate an error checking and checking syndrome using N of the M-bitwords, where N is a positive integer greater than one, the errorchecking and correcting logic further being operable to use the syndrometo check and correct the at least one M-bit word of read data coupled tothe memory controller; and control logic operable to cause the writedata to be coupled to the array of memory cells responsive to the writecommands and to cause the read data to be coupled from the array ofmemory cells responsive to the read commands.
 56. The memory systemclaim 55 wherein the memory controller is operable to: read P M-bitwords from the memory device, where P is a positive integer; combine theP M-bit words read from the memory device with N minus P M-bit words tocreate N M-bit words; and couple the created N M-bit words to the memorydevice to allow the error checking and correcting logic to use thecreated N M-bit words to generate the syndrome.
 57. The memory system ofclaim 56 wherein M is equal to 32, N is equal to 4, and P is equal to 3.58. The memory system of claim 55 wherein the memory controller isoperable to sequentially couple N M-bit words of write data to thememory device.
 59. The memory system of claim 58 wherein M is equal to32, and N is equal to
 4. 60. The memory system of claim 55, furthercomprising a syndrome memory for storing the generated error checkingand checking syndrome, and wherein the error checking and correctinglogic is operable to obtain the syndrome from the syndrome memory foruse in checking and correcting the at least one M-bit word of read datacoupled to the memory controller.
 61. The memory system of claim 60wherein the syndrome memory comprises the same array of memory cells toand from which the at least one M-bit word of write data and read dataare coupled.
 62. The memory system of claim 60 wherein the syndromememory comprises a storage device other than the array of memory cellsto and from which the at least one M-bit word of write data and readdata are coupled.
 63. The memory system claim 55 wherein the memorydevice comprises a DRAM memory device.